ADC_ACLK_EN=ADC_ACLK_EN_0, FLEXIO1_CLK_SEL=FLEXIO1_CLK_SEL_0
CCM Serial Clock Multiplexer Register 2
| FLEXIO1_CLK_SEL | Selector for flexio1 clock multiplexer 0 (FLEXIO1_CLK_SEL_0): derive clock from PLL4 divided clock 1 (FLEXIO1_CLK_SEL_1): derive clock from PLL3 PFD2 clock 2 (FLEXIO1_CLK_SEL_2): derive from PLL2 3 (FLEXIO1_CLK_SEL_3): derive clock from pll3_sw_clk |
| ADC_ACLK_PODF | Divider for ADC alt_clk, as the list below (other values reserved). 7 (ADC_ACLK_PODF_7): pll3_sw_clk / 8 11 (ADC_ACLK_PODF_11): pll3_sw_clk / 12 15 (ADC_ACLK_PODF_15): pll3_sw_clk / 16 |
| ADC_ACLK_EN | Enable ADC alt_clk, so that ADC alt_clk can be driven be divided pll3_sw_clk. 0 (ADC_ACLK_EN_0): ADC alt_clk source is disabled 1 (ADC_ACLK_EN_1): ADC alt_clk source is enabled |